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November 2003 rev 1.0 Features
* * * * * * * * Two on chip PLLs. Generates an EMI optimized clocking signal at output. Non Spread spectrum mode available Input Frequency Range 2MHz- 200Mhz in Non Spread mode Input Frequency Range 6Mhz - 80Mhz in Spread mode. Output Frequency Range 4Mhz - 140Mhz. Four frequency outputs; two per PLL. Programmable spread range and type of modulation ( center or down) and type of profile. * * * Power down feature is incorporated. Both the PLL have reference frequency output. Supply voltage range 3.3 V ( 0.3) Software is available for configuring all the parameters of the Chip, through I2C .
FOUT2_CLK1 PLL1_REF_D2 7 8 FOUT1_CLK1 VDD_FOUT2 VDD_FOUT1 4 5 6 X1OUT VDDA/DIGITAL 2 3 X1IN 1
AS80M2516A
Pin Configuration
16 15 14 13 12 11 10 9
REF1OUT GND SCL SDA FOUT1_CLK2 FOUT2_CLK2 REF2OUT POWER DOWN
*
Product Description
The AS80M2516A is dual phase lock loop clock chip. The AS80M2516A is a versatile spread spectrum frequency modulator design specifically for a wide range of clock frequencies. The AS80M2516A reduces electromagnetic interference (EMI) at clock source. The AS80M2516A allows significant system cost savings by reducing the number of circuit board layers and shielding that are required to pass EMI regulations. The AS80M2516A is I2C configurable. All the
functional parameters of the AS80M2516A can be configured from external I2C master unit through I2C bus. The AS80M2516A modulates the output of PLL in order to spread the bandwidth of a synthesized clock , there by decreasing the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillator and most clock generators. Lowering EMI by increasing a signal's bandwidth is called spread spectrum clock generation.
Alliance Semiconductor 2575, Augustine Drive * Santa Clara, CA * Tel: 408.855.4900 * Fax: 408.855.4999 * www.alsc.com
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.0
AS80M2516A
Block Diagram
X1IN X1OUT
Crystal Oscillator 1 / R PLL1
FOUT1_CLK1
PLL1 MODULATION 1/N Feedback Counter
Out Div
DIV
FOUT1EN CLKGENEN1
FOUT1_CLK2
I 2 C
SDA
Out Div
FOUT2EN CLKGENEN1
SCL
I N T E R F A C E 1 / R PLL2 PLL2
REF1 OUT
DIV 1 2
REFOUT1EN CLKGENEN1
PLL1_REF_D2
FOUT2_CLK1
Out Div
DIV
FOUT1EN CLKGENEN2
FOUT2_CLK2
1/N Feedback Counter
Out Div
FOUT2EN CLKGENEN2
REFOUT2
REFOUT2EN CLKGENEN2
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November 2003 rev 1.0
AS80M2516A
Pin Description Pin Type
IN OUT PWR PWR PWR OUT OUT IN IN OUT OUT OUT IN/OUT IN PWR OUT Connection to Crystal-1 Connection to Crystal-1 Power supply to Analog and Digital blocks except the Output Buffers Variable Output Voltage Control for FOUT2 . The minimum voltage is 1.8V. Variable Output Voltage Control for FOUT1 . The minimum voltage is 1.8V. Tristatable Clock Output-1 of Clock Generator-1 Tristatable Clock Output-2 of Clock Generator-1 Set High to divide the REF_IN(X1IN) by 2 Powers the entire chip down Buffered and Divide by 2 Output of X1IN Tristatable Clock Output-2 of Clock Generator-2 Tristatable Clock Output-1 of Clock Generator-2 Serial Data I/O for I2C Serial Clock Input for I2C Ground to entire chip Buffered Output of X1IN
Pin No
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
X1IN X1OUT VDDA/DIGITAL VDD_FOUT2 VDD_FOUT1 FOUT1_CLK1 FOUT2_CLK1 PLL1_REF_D2 POWERDOWN REF2OUT FOUT2_CLK2 FOUT1_CLK2 SDA SCL GND REF1OUT
Description
Note:- All the Pin types IN have CMOS pull-up resistors.
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November 2003 rev 1.0 Absolute Maximum Ratings
AS80M2516A
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability.
PARAMETER
Supply Voltage, dc (Vss = ground)
SYMBOL
VDD
MIN
VSS-0.5
MAX
7
UNITS
V
Input Voltage, dc
VI
VSS-0.5
VDD+0.5
V
Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI >VDD) Output Clamp Current, dc (VI < 0 or VI >VDD) Storage Temperature Range (non condensing) Ambient Temperature Range, Under Bias Junction Temperature
VO
VSS-0.5
VDD+0.5
V
IIK
-50
50
mA
IOK
-50
50
mA
TS
-65
150
C
TA
-55
125
C
TJ
150
C
Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL - STD 883E, Method 3015.7)
260
C
2
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
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November 2003 rev 1.0
AS80M2516A
Operating Conditions
PARAMETER
Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Serial Data Transfer Rate Output Driver Load Capacitance
SYMBOL
VDD TA FXIN
CONDITIONS/DESCRIPTION
3.3V
MIN
3 0 2
TYP
3.3
MAX
3.6 70 200 100 15
UNITS
V C MHz kb/s pF
10%
Standard mode
10
CL
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November 2003 rev 1.0 DC Electrical Specifications
AS80M2516A
Unless otherwise stated, VDD=3.3V 10%, no load on any output, and ambient temperature range TA=0C to 70C. Parameters with an astertsk (*) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are inclicate current flows out of the device.
3
from typical. Negative currents
PARAMETER
Overall Supply Current, Dynamic Supply Current, Static All input pins High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) High-Level Output Source Current Low-Level Output Source Current High-Level Output Source Current Low-Level Output Sink Current Output Impedance
SYMBOL
CONDITIONS/ DESCRIPTION
MIN
TYP
MAX
UNIT
IDD IDDL
VDD=3.3V, FCLK=50MHz, CL=15pF VDD = 3.3V, powered down via Power Down pin
43 0.3
mA mA
VIH VIL IIH IIL IxOH IxOL
VDD=3.3V VDD=3.3V
2.0 VSS-0.3 -1 -20 -36 21 -21
VDD+0.3 0.8 1 -80 30 -30
V V
A A
mA mA
VDD=V(XIN) = 3.3V, VO=0V VDD=3.3V, V(XIN)=VO=5.5V
10 -10
Clock Outputs (CLK1, CLK2) IOH IOL ZOH ZOL VO=2.4V VO=0.4V VO=0.5VDD; output driving high Vo=0.5VDD; output driving low -20 23 29 27 mA mA
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November 2003 rev 1.0 AC Timing Specifications
AS80M2516A
Unless otherwise stated, VDD = 3.3.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently produciton tested to any specific limits. MIN and MAX characterization data are 3 from typical.
PARAMETER
Overall Output Frequency Rise Time Fall Time Duty Cycle
SYMBOL
CONDITIONS/ DESCRIPTION
VDD = 3.3V VO = 0.3V to 3.0V; CL = 15pF VO = 3.0V to 0.3V; CL = 15pF Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500 s apart at 2.5V relative to an ideal clock, CL = 15pF, fXIN=14.318MHz, FOUT =
CLOCK (MHz)
MIN
TYP
MAX
UNIT
fo tr Tf
4 2.1 1.9
140
MHz ns ns
Clock Outputs (PLL A clock via FOUT1_CLK1/FOUT2_CLK1 pins) 100 45 55 %
100
45
Jitter, Long Term (y())*
Tj(LT)
50MHz, PLL-B inactive. On rising edges 500 s apart at 2.5V relative to an ideal clock, CL = 15pF, fXIN=14.318MHz, FOUT = 50MHz, PLL -B active (60MHz) From rising edge to the next rising edge at 2.5V, CL = 15pF, fXIN=14.318MHz, FOUT = 50MHz 100 110 ps 50 165
Jitter, Period (peak-peak)
Tj(P)
PLL-B inactive. From rising edge to the next rising edge at 2.5V, CL = 15pF, fXIN=14.318MHz, FOUT = 50MHz PLL-B active (60MHz) 50 390
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November 2003 rev 1.0 AC Timing Specifications (Continued)
AS80M2516A
Unless otherwise stated, VDD = 3.3.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently produciton tested to any specific limits. MIN and MAX characterization data are 3 from typical.
CONDITIONS/ CLOCK DESCRIPTION (MHz) Clock Outputs (PLL B clock via FOUT1_CLK2 / FOUT2_CLK2 pins) Duty Cycle Ratio of pulse width (as measured from rising edge to 100 next falling edge at 2.5V) to one clock period On rising edges 500 s apart at 2.5V relative to an ideal clock, Jitter, Long CL = 15pF, fXIN=14.318MHz, Tj(LT) 100 Term (y())* FOUT = 50MHz , PLL -A inactive. On rising edges 500 s apart at 2.5V relative to an ideal clock, CL = 15pF, fXIN=14.318MHz, 60 FOUT = 50MHz, PLL -A active (60MHz) From rising edge to the next Jitter, Period rising edge at 2.5V, CL = 15pF, Tj(P) 100 (peak-peak) fXIN=14.318MHz, FOUT = 50MHz PLL-B inactive. From rising edge to the next rising edge at 2.5V, CL = 15pF, 60 fXIN=14.318MHz, FOUT = 50MHz PLL-A active (50MHz) Clock Otput active from power up, Stabilization tSTB RUN Mode via Power Down Time pin
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
45
55
%
45
ps
75
120
ps
400
100
ns
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November 2003 rev 1.0
AS80M2516A
Modulation Domain Analyser Snapshot of 75MHz 0.75% Deviation Clock
Spectrum Analyser Snapshot of 75MHz 0.75% Deviation Clock
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November 2003 rev 1.0 General I2C Serial Interface Information
The information in this section assumes familiarity with I2C programming. How to Write through I2C : * * * * * * * * * * Master (host) sends a start bit. Master (host) sends the write address XX (H) AS80M2516A device will acknowledge Master (host) sends a dummy command code AS80M2516A device will acknowledge Master (host) sends a dummy byte count AS80M2516A device will acknowledge Master (host) starts sending first byte (Byte 0) through byte N - 1 AS80M2516A device will acknowledge each byte one at a time. Master (host) sends a Stop bit AS80M2516A (slave/receiver) Controller (Host) ACK Dummy Command Code ACK Dummy byte count ACK First byte (Byte 0) ACK Second Byte (Byte 1) ACK ---------Last Byte (Bye N-1) ACK Stop Bit Not Acknowledge Stop Bit ------ACK ACK ACK Start Bit Slave Address XX(H) * * How to Read through I2C: * * * * * *
AS80M2516A
Master (host) will send start bit. Master (host) sends the read address XX (H) AS80M2516A device will acknowledge AS80M2516A device will send the byte count Master (host) acknowledges AS80M2516A device sends first byte (Byte 0) through byte N - 1 Master (host) will need to acknowledge each byte Master (host) will send a stop bit (* N is the number of bytes)
Controller (Host) Start Bit Slave Address XX(H)
AS80M2516A (slave/receiver)
ACK Date Byte Count First byte (Byte 0) Second Byte (Byte 1) ---Last Byte (Bye N-1)
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November 2003 rev 1.0
Software A demonstration board and software is available for the AS80M2516A. The software can operate under Windows 95 and Windows NT. The opening screen of the software is shown in figure 2.
AS80M2516A
By pressing the drop down arrow of Port ID toolbar button ,any of the three parallel ports ( LPT1 LPT2 or LPT3 ) can be selected. The selected parallel port is used for the I2C data transfer.
Opening screen
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November 2003 rev 1.0
Programming the PLLs:Select the CGEN check box to enable the PLL and the EMI reduction check box to enable the spread spectrum on. Enter the input frequency (in Mhz) , output frequency (Mhz) , percentage error and modulation rate (Khz) in the respective input boxes. To enable the OUT1 OUT2 and REFOUT click the respective check box. To tristate all the outputs click the tristate check box. Select the type of the modulation between the center or down and enter the deviation (percentage ) in the respective input box. Profile type can be selected between the sine triangular or lexmark. EMI reduction enable/disable option is only available for the PLL1. 7. Writing the data to the chip :There are two different ways of writing data to the chip. 1. Writing through the file. 2. Enter the required data in the respective forms and calculate and then write. For Example: 6. 5. 4. 3. 1. 2.
AS80M2516A
Enter the input freq say 15 Mhz, in the input frequency box. Enter the required output frequency say 65 Mhz, in the out1 frequency box. Enter the percentage error say 0.01 in the error box. Enter the modulation rate say 30 khz in the modulation rate box. Select the second output frequency by pressing the pull down menu of the out2 frequency. The value of OUT2 frequency can be selected as vco/2 , vco/3 , vco/4 , vco/5 , vco/6 , vco/8 , vco/9 , vco/10 , vco/12 , vco/15 , vco/18 , vco/24 or vco/30. Select the type of the deviation , percentage deviation and type of the profile. Enter the data for PLL2 in a similar manner.
8. 9.
Press the CalcResult button to load the data in the ROM data panel. To write this data to the chip press the I2CWrite button.
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November 2003 rev 1.0
AS80M2516A
Results Window Reading the data from the Chip 1. 2. 3. To read the data from the chip through I2C , press the I2CRead button. The data can be seen in the rom data field. This data which is read from the chip can be saved in the file by clicking the Save button .
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November 2003 rev 1.0
AS80M2516A
Package Information
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November 2003 rev 1.0
AS80M2516A
Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Preliminary Information Part Number: AS80M2516A Document Version: v1.0
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in lifesupporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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